1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device that determines a write pulse width timing.
2. Background of the Related Art
FIG. 1 is a block diagram showing a related art semiconductor memory device. The related art semiconductor memory device includes a WCD signal generating part 11 outputting a logical product, which is a write control driving signal WCD, upon application of a write enable signal WET from a pad PAD (not shown). A WCDN generating part 13 produces a signal WCDN for controlling a data input part upon receipt of the WCD signal, a chip selection signal CS, and a signal Z-DEC. A data input part 15 outputs a logical product, which is high-level data and low-level data, to a corresponding memory cell upon application of the write enable signal WET from the pad PAD.
The signal Z-DEC informs the WCDN generating part 13 which cell of cells defined by blocks is selected. The WCD signal generating part 11 includes an inverter INT1 inverting the applied write enable signal WET, and an inverter INT2 inverting a signal output from inverter INT1. A NAND gate NAND1 outputs a logical product of an output signal of inverter INT2 and write enable signal WET, and an inverter INT3 inverts an output signal of the NAND gate NAND1.
The data input part 15 includes an inverter INT4 inverting applied data, a NOR gate NOR1 performing a NOR operation with respect to an output signal of inverter INT4 and the WCDN signal, and a NOR gate NOR2 performing a NOR operation with respect to the applied data signal and the WCDN signal. Inverters INT5 and INT6 respectively invert an output signal of each of the NOR gates NOR1 and NOR2, and an inverter INT7 inverts an applied signal CWEN. A transfer gate TG1 is interposed between input and output terminals of the inverter INT7, and a transfer gate TG2 is connected in series to the transfer gate TG1.
The transfer gate TG1 produces high-level data, and the transfer gate TG2 outputs low-level data. The signal CWEN is a control signal and serves to turn on transfer gates TG1 and TG2 when storing data in a cell.
The operation of the related art memory device will now be described. As shown in FIGS. 2A-2E, the WCD signal generating part 11 generates the write control driving signal WCD upon application of the write enable signal WET from the pad PAD. When comparing the point of disabling write enable signal WET to that of disabling write control drive signal WCD, there exists a delay time td. The write control driving signal WCD is an internal enable signal WCD necessary for writing data to a cell. Thus, the width of write control driving signal WCD and the points (i.e., timing) of enabling and disabling the WCD signal are important.
The WCDN generating part 13 transmits the signal WCDN to the data input part 15 upon application of the signals WCD and Z-DEC, which is not depicted in FIG. 2. The data input part 15 writes data to a selected cell under control of the signal WCDN. Accordingly, it is necessary to either advance the point of enabling signal WCD or delay the point of disabling signal WCD to improve the accuracy and speed of the write pulse timing. Delaying the point of the disabling signal WCD causes a delay in the point of disabling the signal WCDN, which adversely affects the write recovery timing. As described above, the write pulse width timing (WPT) may be improved by advancing the point of enabling signal WCD but this technique also has a restriction. The enabling point cannot be advanced too much because of the address setup time. In conclusion, the point of writing data to a cell equals the time when the WCDN generating part 13 produces the signal WCDN on receipt of the signal WCD.
In a case where the power supply voltage transitions to a low level, the point of disabling signal WCD cannot be delayed. In repetition of data write and data read, it is required to disable the signal WCD as soon as possible. Otherwise, the data write timing changes to the data read timing even though writing data to a cell is not completely finished. Thus, delaying the point of the disabling signal WCD adversely affects the write recovery timing.
The above-described related art semiconductor memory device has various disadvantages. In the related art semiconductor memory device there is a time margin or period in the write recovery timing when the power supply voltage attains a low level compared to when the power supply voltage attains a high level, and it is necessary to advance the point of enabling signal WCD in order to compensate for a write pulse width timing (TWP). However, there is a limit to advancing the point of enabling signal WCD because of the address setup timing, which makes it impossible to realize a high speed static random access memory. Further, in the related art device, the points of enabling and disabling signal WCD are not controlled according to the power supply voltage level, which reduces the efficiency of the semiconductor memory device.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.